1. Field of the Invention
This invention pertains to a semiconductor memory device comprising a memory cell array formed by a plurality of memory cell arrays arranged in a matrix form, in which the datum stored in a selected memory cell is read out through a pair of bit lines provided at each column of the memory cell array, a sense amplifier, a readout column gate, and a pair of data buses provided commonly for columns of the memory cell array.
2. Description of the Related Arts
FIG. 1 is a schematic circuit diagram of a conventional semiconductor memory device.
It shows, as an example, a dynamic random access memory (DRAM) in which a memory cell array 1 comprises a memory cell 2, an nMOS transistor 3, and a capacitor 4. The nMOS transistor 3 forms a cell selection switch, and the capacitor 4 forms a memory element.
The memory cell array 1 is connected to a row decoder 5 though a word line WL. BL and BLX are a pair of bit lines. 6 is a sense amplifier (S/A). A column gate 7 comprises nMOS transistors 8 and 9.
nMOS transistors 10 and 11 respectively for data buses DB and DBX are provided commonly for the columns of the memory cell array 1. 12 is a Vcc power supply, 13 is a data bus amplifier, CL is a column selection line, 14 is a column decoder, 15 is a column driver comprising a CMOS inverter, 16 is a pMOS transistor, and 17 is an nMOS transistor.
The pair of bit lines BL and BLX are precharged to Vci [=(Vcc-Vth)/2] [V], where Vcc is a power supply voltage and Vth is the threshold voltage of an nMOS transistor. All the nMOS transistors 3, 10, 11 and 17 are formed simultaneously and therefore have the same threshold voltage Vth. The column selection line CL with the power supply voltage Vcc [V] applied at a nonselection turns the pMOS transistor 16 ON and nMOS transistor 17 of the column driver 15 OFF. The column selection line CL with 0.0 [V] applied at a selection turns the pMOS transistor 16 OFF and nMOS transistor 17 of the column driver 15 ON.
FIG. 2 is a time chart for explaining the operations of the semiconductor memory device shown in FIG. 1.
When a high voltage (i.e. a "1" level) is stored in the capacitor 4 of the memory cell 2 of this DRAM, a selection of the memory cell 2 drives the word line WL and turns ON nMOS transistor 3. The high voltage (i.e. a "1" level) stored in the capacitor 4 of the memory cell 2 slightly raises the voltage of bit line BL. At this time, the voltage of bit line BLX remains the same.
A sense amplifier 6 is driven next to raise the voltage of bit line BL to Vci [V] and to lower the voltage of bit line BLX to 0.0 [V]. Then, the column decoder 14 drives the column selection line CL and turns ON nMOS transistors 8 and 9, thereby connecting bit lines BL and BLX respectively to data buses DB and DBX. As a result, the voltages of both bit line BL and data bus DB rise to Vci [V], while the voltages of both bit line BLX and data bus DBX fall to 0.0 [V]. The data bus amplifier 13 detects the changes in the voltages of the data buses DB and DBX, thereby allowing the high voltage (i.e. the "1" level) data to be read out, during which a current I flows from the Vcc power supply 12 to ground through nMOS transistor 11, data bus DBX, nMOS transistor 9, bit line BLX and the sense amplifier 6.
On the other hand, when a low voltage (i.e. a "0" level) is stored in the capacitor 4 of the memory cell 4, nMOS transistor 3 of the memory cell 2 being turned ON lowers the voltages of both bit line BL and data bus DB to 0.0 [V] and raises the voltages of both bit line BLX and data bus DBX to Vci [V].
To summarize the above, the DRAM has the content stored in the capacitor 4 of memory cell 2 to be read out through the bit lines BL and BLX, the sense amplifier 6, the column gate 7, the data buses DB and DBX, and the data bus amplifier 13.
However, the conventional DRAM shown in FIG. 1 does not allow the column gate 7 to be driven before driving the sense amplifier 6 because of its possible malfunctioning due to a dampening of an output signal from the memory cell 2 caused by the selection of the column gate 7 before driving the sense amplifier 6. This is because the capacitance of bit line BL for the memory cell 2 becomes the sum of the parasitic capacitance of bit line BL and that of data bus DB, which is about ten [10] times larger, if the column gate 7 is selected before driving the sense amplifier 6.
Also, the conventional DRAM shown in FIG. 1 does not allow the column gate 7 to be driven even after driving the sense amplifier 6 until the voltage differences from the bit lines BL and BLX reach a certain value. This is because the noises from the data buses DB and DBX (the voltages applied to the data buses DB and DBX) may cause the sense amplifier 6 to malfunction.
Hence, the conventional DRAM shown in FIG. 1 needs to be selected only after the voltage difference between the bit lines BL and BLX reaches a certain value. This results in a problem of requiring a certain amount of time before selecting the column gate 7 after driving the sense amplifier 6, which delays its access.
FIG. 3 is a schematic circuit diagram of another conventional semiconductor memory device.
This shows the configuration of a DRAM for correcting the above described problem of the conventional DRAM shown in FIG. 1. Parts shown in FIG. 3 which are the same as those shown in FIG. 1 have the same numbers.
The DRAM shown in FIG. 3 has a readout column gate 18 and a write-in column gate 160 in lieu of the column gate 7 for the DRAM shown in FIG. 1. The readout column gate 18 comprises four [4] nMOS transistors 19, 20, 21 and 22, and the write-in column gate 160 comprises two [2] transistors 161 and 162.
nMOS transistor 19 has connections with bit line BL at its gate, with readout data bus DBR at its drain D, and with a drain D of nMOS transistor 20 at its source S. nMOS transistor 20 has connections with readout column selection line CLR at its gate, and with ground at its source S.
Furthermore, nMOS transistor 21 has connections with bit line BLX at its gate, with readout data bus DBRX at its drain D, and with drain D of nMOS transistor 22 at its source S. nMOS transistor 22 has connections with readout column selection line CLR at its gate, and with ground at its source S.
In addition, nMOS transistor 161 has connections with write-in column selection line CLW at its gate, with bit line BL at its source S, and with write-in data bus DBWX at its drain D. nMOS transistor 162 has connections with write-in column selection line CLW at its gate, with bit line BLX at its source S, and with write-in data bus DBW at its drain D.
As a result of reconfiguring the column gate 7 shown in FIG. 1 into the readout column gate 18 and the write-in column gate 160, on turning ON the readout column gate 18, the capacitance of bit line BL for memory cell 2 is equal only to the parasitic capacitance of bit line BL. Thus, unlike the conventional DRAM shown in FIG. 1, the conventional DRAM shown in FIG. 3 causes no effect due to the parasitic capacitance of data bus DB on the output voltage of the memory cell 2, thereby preventing output voltage of the memory cell 2 from being dampened.
Also, because the readout data buses DBR and DBRX does not connect to the readout column gate 18 through the sense amplifier 6, no matter what voltages the readout data busses DBR and DBRX carry before selecting the readout column gate 18, they have no effects on the sense amplifier 6.
As a result, the time difference between the timing for driving the sense amplifier 6 and that for driving the readout column gate 18 can be more liberally set. This in turn expedites a selection of the readout column gate 18 after driving the sense amplifier 6, thereby enabling a fast DRAM access.
Besides, the sense amplifier 6 need only drive the bit lines BL and BLX and need not drive readout data buses DBR and DBRX. Thus, the bit lines BL and BLX can rise and fall more rapidly, which is also instrumental in expediting the access.
However, the conventional DRAM shown in FIG. 3 has a problem of an increased chip area, because it is difficult to compactly arrange the large number of transistors forming the readout column gate 18 in a tiny chip in view of their interconnecting structures.
Because the readout column gate 18 and the writein column gate 160 need to be provided at each column, the problem of the increased chip area must be solved to miniaturize such a chip.